1. Field of the Invention
The present invention relates to a phase locked loop circuit (called a "PLL circuit" in this specification), and more specifically to a phase locked loop circuit having large capture range and a high stability.
2. Description of Related Art
Referring to FIG. 5, there is shown a block diagram of a conventional PLL circuit. The PLL shown circuit includes a phase/frequency comparing circuit (PFD) 3 having one input connected to receive an input signal 1, a charge pump 4 receiving an UP signal 11 and a DOWN signal 12 from the phase/frequency comparing circuit 3, a loop filter (low pass filter, LPF) 5 having an input connected to an output of the charge pump 4, and a voltage controlled oscillator (VCO) 2 having an input connected to an output of the loop filter 5 and an output connected to the other input of the phase/frequency comparing circuit 3.
The phase/frequency comparing circuit 3 compares the input signal 1 with the output signal of the voltage controlled oscillator 2 in phase or in frequency, and outputs the UP signal 11 and the DOWN signal 12 which are a pulse signal having a width corresponding to a phase difference or a frequency difference between the input signal 1 with the output signal of the voltage controlled oscillator 2. The charge pump 4 is configured so that when the UP signal 11 is active, an internal charging switch (not shown) is put in an ON condition so as to charge an internal capacitor (not shown) during an ON period of the internal charging switch, and when the UP signal 11 is inactive, the internal charging switch is put in an OFF condition to maintain the potential of the internal capacitor, and further when the DOWN signal 12 is active, an internal discharging switch (not shown) is put in an ON condition so as to discharge the internal capacitor during an ON period of the internal discharging switch, and when the down signal 12 is inactive, the internal discharging switch is put in an OFF condition to maintain the potential of the internal capacitor. Therefore, the electric charge stored in the internal capacitor of the charge pump 4 is selectively charged, discharged or maintained in accordance with the UP signal 11 and the DOWN signal 12.
The loop filter 5 smoothes the voltage which varies depending upon the charging/discharging of the electric charge stored in the charge pump. In accordance with an output voltage of the loop filter 5, the voltage controlled oscillator 2 controls the frequency of the oscillation of the voltage controlled oscillator 2 so as to make the phase or frequency difference between the input signal 1 and the oscillation signal outputted from the voltage controlled oscillator 2 zero.
In general, when the PLL circuit is used for generating a clock for a system including a digital circuit, a capture range of the PLL circuit is required to be large in order to supply a clock in all possible modes that the system can assume.
For example, Japanese Patent Application Pre-examination Publication No. JP-A-04-070122, (an English abstract of JP-A-04-070122 is available from the Japanese Patent Office and the content of the English abstract of JP-A-04-070122 is incorporated by reference in its entirety into this application) discloses one prior art PLL circuit configured to enlarge the capture range of the PLL circuit. Referring to FIG. 6, there is shown a block diagram of this prior art PLL circuit.
In FIG. 6, elements similar to those shown in FIG. 5 are given the same Reference Numerals, and an explanation thereof will be omitted. As shown in FIG. 6, this prior art PLL circuit includes a counter 6 for counting an arbitrary clock CK from a clock circuit 18, a register 24 for latching and holding the value of the counter 6, and a current switch circuit 7 for supplying a current adjusted in accordance with the value held in the register 24, to one input of an analog adder 27, which has the other input connected to the output of the loop filter 5 and an output connected to the input of the voltage controlled oscillator 2. This shown prior art PLL circuit also includes a reset circuit 8 for resetting the counter 6 and the register 24, a reference voltage circuit 20 for generating a first reference voltage V.sub.RO and a second reference voltage V.sub.R, a comparator 21 for comparing the output voltage of the loop filter 5 with the reference voltage V.sub.R to output a control signal, a timing circuit 22 responding to the control signal from the comparator 21 to control a switch 23 which controls the counter 6 and the register 24.
Now, an operation of the prior art PLL circuit shown in FIG. 6 will be described with reference to FIG. 6 and FIG. 7 which is a timing chart illustrating a relation between an error voltage and control signals in the prior art PLL circuit shown in FIG. 6. Here, the first reference voltage V.sub.RO corresponds to a voltage supplied to the voltage controlled oscillator 2 when the voltage controlled oscillator 2 oscillates at an center frequency of the capture range of the PLL circuit, and the second reference voltage V.sub.R is defined as V.sub.R =(V.sub.RO -.DELTA.V) where .DELTA.V is an offset value. A minimum value of the current supplied from the current switch circuit 7 corresponds to a voltage supplied to the voltage controlled oscillator 2 when the voltage controlled oscillator 2 oscillates at a low frequency out of the capture range of the PLL circuit.
First, when it is powered on, the counter 6 and the register 24 are reset by a reset signal RESET from the reset circuit 8. After the counter 6 is reset, the counter 6 starts to count up the clock CK from the clock circuit 18, and the count value of the counter 6 is latched by the register 24 at each clock, so that the current switch circuit 7 supplies a current in proportion to the count value of the counter 6. Namely, the current outputted from the current switch circuit 7 gradually increases in proportion to the count value of the counter 6. In accordance with the increasing current, the free-running frequency of the voltage controlled oscillator 2 gradually elevates from the low frequency out of the capture range of the PLL circuit, so that the oscillating frequency ultimately comes within the capture range of the PLL circuit, and the PLL circuit is put in a locked condition.
On the other hand, as shown in FIG. 7, the phase/frequency comparing circuit 3 outputs an error signal corresponding to the first reference voltage V.sub.RO when the frequency of the output signal of the voltage controlled oscillator 2 is out of the capture range of the PLL circuit, and outputs the error signal corresponding to the frequency difference between the input signal 1 and the output signal of the voltage controlled oscillator 2 when the frequency of the output signal of the voltage controlled oscillator 2 comes within the capture range of the PLL circuit. Therefore, at this time, the phase/frequency comparing circuit 3 starts to output the error signal lower than the second reference voltage V.sub.R, and the comparator 21 outputs the control signal of a low level.
After the PLL circuit is put in the locked condition, if the current outputted from the current switch circuit 7 increases, the error voltage outputted from the phase/frequency comparing circuit 3 increases as shown in FIG. 7. When the output of the loop filter 5 reaches the second reference voltage V.sub.R, the output of the comparator 21 is brought to a high level, which brings the output of the timing circuit 22 into a low level, which controls the switch 23 to the effect that the register 24 no longer latches a new count value of the counter 6 and the output current of the current switch circuit 7 is fixed to the value designated by the content held in the register 24. Thereafter, only the control loop of the PLL circuit operates.
In the above mentioned prior art PLL circuit, the free-running frequency of the voltage controlled oscillator 2 is forcibly changed from the low frequency out of the capture range of the PLL circuit, and when the free-running frequency of the voltage controlled oscillator 2 comes within the capture range of the PLL circuit, the PLL circuit is controlled by detecting the change of the error voltage. Therefore, the capture range can be substantially enlarged.
However, since the above mentioned prior art PLL circuit requires the reference voltage circuit 20 and the comparator 21, the circuit scale becomes large. In addition, since the above mentioned prior art PLL circuit is sensitive to the temperature variation and to the power supply voltage variation, the capture range cannot be enlarged because it is necessary to compensate for the sensitivity problem, and therefore, it is difficult to improve the jitter amount.